Mojo FPGA Development Board Shield: 3 Kauj Ruam

2024 Tus sau: John Day | [email protected]. Kawg hloov kho: 2024-01-30 09:26

Txuas koj Mojo pawg thawj coj txhim kho rau sab nraud nkag nrog cov ntaub thaiv npog no.

Mojo pawg tswj hwm kev txhim kho yog dab tsi?

Mojo pawg thawj coj txhim kho yog pawg thawj coj txhim kho raws li Xilinx spartan 3 FPGA. Lub rooj tsavxwm yog tsim los ntawm Alchitry. FPGA's muaj txiaj ntsig zoo nyob qhov twg ntau cov txheej txheem yuav tsum tau ua tiav ib txhij.

Koj yuav xav tau dab tsi?

Khoom siv

Mojo txoj kev loj hlob board

Gerber ntawv

8 x 15k ohm resistors (yeem*)

4 x 470 ohm resistors

4 x 560 ohm resistors

4 x CC xya ntu qhia tawm

4 x 3mm LEDs

4 x SPDT tactile keyboards

1 x 4 txoj hauj lwm nto mount DIP hloov

2 x 25 los ntawm 2 lossis 4 x 25 headers

1x2 los ntawm 5 tus pin lub taub hau lub taub hau

Soldering hlau

Solder

Dej ntws

*(yog tias cov resistors no raug rho tawm sab hauv rub tawm/rubldown yuav tsum tau qhib rau cov pins cuam tshuam)

Kauj Ruam 1: Upload Gerber rau Pcb Chaw Tsim Khoom ntawm Koj Qhov Kev Xaiv

Rau kuv cov laug cam kuv xaj los ntawm JLC PCB.

Qhov kev hloov pauv nkaus xwb kuv tau ua yog xim uas kuv xav kom phim dub ntawm Mojo.

Kauj Ruam 2: Pawg Rooj Sib Tham

Thaum siv cov tshuaj txhuam kuv ib txwm pom tias nws muaj txiaj ntsig zoo los txhawm rau ua qhov qis tshaj ua ntej yog li pib nrog cov tshuaj tiv thaiv yog lub tswv yim zoo.

R5, R6, R7, R8, R9, R10, R11 thiab R12 yog 15k ohm resistors siv los rub cov hloov pauv (yog tias koj siv sab hauv rub tawm/pulldown tsis quav ntsej qhov no).

R1, R2, R3, R4 yog 560 ohm resistors uas yog lub luag haujlwm rau txwv qhov tam sim no los ntawm 7 ntu tso saib.

R13, R14, R15, R16 yog 470 ohm resistors uas yog lub luag haujlwm txwv qhov tam sim no los ntawm 4 LED's.

Tom ntej solder lub dip hloov, hloov tactile, LED's, xya ntu qhia thiab lub thawv header txuas hauv qhov kev txiav txim.

Tam sim no tso 25 los ntawm 2 (lossis 2 25 los ntawm 1) rau hauv mojo txhawm rau kho tus pin. Teem daim thaiv nrog cov pins thiab muab nws tso rau hauv qhov chaw.

Kauj ruam 3: Teeb Software

Txog software hais txog Alchitry lub vev xaib yuav qhia rau koj paub tias koj xav tau dab tsi los pib thiab teeb tsa Xilinx ISE. Txawm li cas los hloov cov ntaub ntawv.ucf yog li nws paub tias pins txuas nrog dab tsi tseem ceeb kom tau txais koj cov haujlwm.

Nov yog.ucf cov ntaub ntawv kuv siv nrog daim ntaub thaiv:

CONFIG VCCAUX = 3.3;

NET "clk" TNM_NET = clk; TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%; NET "clk" LOC = P56 | IOSTANDARD = LVTTL; NET "rst_n" LOC = P38 | IOSTANDARD = LVTTL; NET "cclk" LOC = P70 | IOSTANDARD = LVTTL; NET "spi_mosi" LOC = P44 | IOSTANDARD = LVTTL; NET "spi_miso" LOC = P45 | IOSTANDARD = LVTTL; NET "spi_ss" LOC = P48 | IOSTANDARD = LVTTL; NET "spi_sck" LOC = P43 | IOSTANDARD = LVTTL; NET "spi_channel" LOC = P46 | IOSTANDARD = LVTTL; NET "spi_channel" LOC = P61 | IOSTANDARD = LVTTL; NET "spi_channel" LOC = P62 | IOSTANDARD = LVTTL; NET "spi_channel" LOC = P65 | IOSTANDARD = LVTTL; NET "avr_tx" LOC = P55 | IOSTANDARD = LVTTL; NET "avr_rx" LOC = P59 | IOSTANDARD = LVTTL; NET "avr_rx_busy" LOC = P39 | IOSTANDARD = LVTTL; NET "Q [0]" LOC = P26 | IOSTANDARD = LVTTL; NET "Q [1]" LOC = P23 | IOSTANDARD = LVTTL; NET "Q [2]" LOC = P21 | IOSTANDARD = LVTTL; NET "Q [3]" LOC = P16 | IOSTANDARD = LVTTL; NET "S [0]" LOC = P7 | IOSTANDARD = LVTTL; NET "S [1]" LOC = P9 | IOSTANDARD = LVTTL; NET "S [2]" LOC = P11 | IOSTANDARD = LVTTL; NET "S [3]" LOC = P14 | IOSTANDARD = LVTTL; NET "pb [1]" LOC = P30 | IOSTANDARD = LVTTL; NET "pb [2]" LOC = P27 | IOSTANDARD = LVTTL; NET "pb [3]" LOC = P24 | IOSTANDARD = LVTTL; NET "pb [4]" LOC = P22 | IOSTANDARD = LVTTL; NET "sevsega [0]" LOC = P57 | IOSTANDARD = LVTTL; NET "sevsegb [0]" LOC = P58 | IOSTANDARD = LVTTL; NET "sevsegc [0]" LOC = P66 | IOSTANDARD = LVTTL; NET "sevsegd [0]" LOC = P67 | IOSTANDARD = LVTTL; NET "sevsege [0]" LOC = P74 | IOSTANDARD = LVTTL; NET "sevsegf [0]" LOC = P75 | IOSTANDARD = LVTTL; NET "sevsegg [0]" LOC = P78 | IOSTANDARD = LVTTL; NET "sevsegdp [0]" LOC = P80 | IOSTANDARD = LVTTL; NET "sevsega [1]" LOC = P82 | IOSTANDARD = LVTTL; NET "sevsegb [1]" LOC = P83 | IOSTANDARD = LVTTL; NET "sevsegc [1]" LOC = P84 | IOSTANDARD = LVTTL; NET "sevsegd [1]" LOC = P85 | IOSTANDARD = LVTTL; NET "sevsege [1]" LOC = P87 | IOSTANDARD = LVTTL; NET "sevsegf [1]" LOC = P88 | IOSTANDARD = LVTTL; NET "sevsegg [1]" LOC = P92 | IOSTANDARD = LVTTL; NET "sevsegdp [1]" LOC = P94 | IOSTANDARD = LVTTL; NET "sevsega [2]" LOC = P97 | IOSTANDARD = LVTTL; NET "sevsegb [2]" LOC = P98 | IOSTANDARD = LVTTL; NET "sevsegc [2]" LOC = P99 | IOSTANDARD = LVTTL; NET "sevsegd [2]" LOC = P100 | IOSTANDARD = LVTTL; NET "sevsege [2]" LOC = P101 | IOSTANDARD = LVTTL; NET "sevsegf [2]" LOC = P102 | IOSTANDARD = LVTTL; NET "sevsegg [2]" LOC = P104 | IOSTANDARD = LVTTL; NET "sevsegdp [2]" LOC = P111 | IOSTANDARD = LVTTL; NET "sevsega [3]" LOC = P114 | IOSTANDARD = LVTTL; NET "sevsegb [3]" LOC = P115 | IOSTANDARD = LVTTL; NET "sevsegc [3]" LOC = P116 | IOSTANDARD = LVTTL; NET "sevsegd [3]" LOC = P117 | IOSTANDARD = LVTTL; NET "sevsege [3]" LOC = P118 | IOSTANDARD = LVTTL; NET "sevsegf [3]" LOC = P119 | IOSTANDARD = LVTTL; NET "sevsegg [3]" LOC = P1120 | IOSTANDARD = LVTTL; NET "sevsegdp [3]" LOC = P121 | IOSTANDARD = LVTTL;

Nco ntsoov yog tias koj tsis tau teeb tsa lub pulldown resistors los hloov cov pins hauv.ucf nrog

| QAUV; o

| QAUV;

Yog tias koj xav siv qhov thaiv rau txhua yam kev sib txuas yog raws li hauv qab no. Sab laug yog tus lej tus lej thaiv thiab sab xis yog tus lej tus lej mojo uas koj yuav tsum tau muab rau hauv koj.ucf:

pin 1 = 29

pin 2 = 51

pin 3 = 32

pin 4 = 41

pin 5 = 34

pin 6 = 35

pin 7 = 40

pin 8 = 33

pin 9 = GND

pin 10 = V