FPGA Cyclone IV DueProLogic Tswj Raspberry Pi Lub Koob Yees Duab: 5 Kauj Ruam

2024 Tus sau: John Day | [email protected]. Kawg hloov kho: 2024-01-30 09:24

Txawm hais tias FPGA DueProLogic tau tsim los rau Arduino, peb tab tom ua FPGA thiab Raspberry Pi 4B sib txuas tau.

Peb txoj haujlwm tau ua tiav hauv qhov kev qhia no:

(A) Ib txhij nias ob lub laub khawm ntawm FPGA txhawm rau lub kaum sab xis ntawm RPi lub koob yees duab.

(B) Raspberry Pi 4B tswj cov LED sab nrauv ntawm FPGA.

(C) Nyob kwj Raspberry Pi Lub Koob Yees Duab ntawm Browser ntawm WiFi

Kauj Ruam 1: Tsim Cov Hluav Taws Xob Hluav Taws Xob

Kauj ruam 2: Kho Verilog Code

Thaum koj yuav FPGA DueProLogic, koj yuav tsum tau txais daim DVD. Tom qab koj qhib "Projects_HDL", koj yuav tsum pom daim ntawv HDL thawj daim ntawv. Tom qab koj teeb tus pin tus phiaj xwm, ntxiv cov lej tseem ceeb raws li qhia hauv ntu 2A, 2B, 2C thiab 2D.

2A: Txhawm rau qhib lub laub khawm, koj yuav tsum siv tus lej no

// Laub khawm Hloov

input hlau UBA,

input hlau UBB

Txhawm rau sib tham nrog Raspberry Pi, koj yuav tsum tau ntxiv cov no.

reg sel_send; // qhib Raspberry pi

reg tau; // tau txais los ntawm raspberry pi

2B: Txhawm rau muab cov txiaj ntsig rau cov chaw nres nkoj, koj yuav tsum hloov kho cov cai kom raug

muab XIO_1 [3] = start_stop_cntrl;

muab XIO_2 [2] = tau txais; // tso zis siab lossis qis hauv LED Circuit

muab XIO_2 [3] = ~ UBA; // laub khawm

assign XIO_2 [4] = UBB; // laub khawm

muab XIO_2 [5] = sel_send; // FPGA xa teeb liab mus rau raspberry pi

muab sel_read = XIO_5 [1]; // FPGA tau txais teeb liab los ntawm raspberry pi

muab c_enable = XIO_5 [2]; // XIO_5 - UB57 - D17

muab LEDExt = XIO_5 [5];

2C: Yog tias ob lub khawm thawb raug nias ib txhij, FPGA xa HIGH cov zis rau Raspberry Pi.

ib txwm @(sel_send lossis UBB lossis UBA) // xa mus rau RPi

pib

yog (UBB == 1'b0 && UBA == 1'b0)

sel_send = 1'b1;

lwm tus

sel_send = 1'b0;

kawg

2D: FPGA nyeem teeb liab los ntawm Raspberry Pi nrog lub moos zaus ntawm 66MHz. Chaw nres nkoj XIO_2 [2] txuas nrog 'txais'.

ib txwm @(sel_read) // nyeem pi

pib

yog (sel_read == 1'b1)

tau = 1'b0;

lwm tus

tau = 1'b1;

kawg

Kauj ruam 3: Upload Verilog Code

Tom qab ntawv rub cov ntawv pof ua ke mus rau FPGA. Yog tias tsis muaj kev kho vajtse raug kuaj pom, nyem "Teeb Kho Vajtse" los kho nws tus kheej

Kauj ruam 4: Upload Raspberry Pi Code

Cov kab ntawv tseem ceeb tso cai rau FPGA sib tham nrog Raspberry Pi.

Tus lej Raspberry Pi tag nrho rau txoj haujlwm no,

A = GPIO.input (tus pin) #read FPGAprint (A);

yog tias (A == 1):

camera.rotation = 0

GPIO.output (18, GPIO. LOW) #xa mus rau FPGA

yog tias (A == 0):

camera.rotation = 180

GPIO.output (18, GPIO. HIGH) #xa mus rau FPGA

Kauj Ruam 5: Cia Sim Sim

Qhib koj tus browser thiab ntaus koj tus IP chaw nyob xws li 192.168.xx.xxx: 8000.

Tom qab tag nrho, lub kaw lus yuav tsum ua haujlwm!